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NOUN TMA PHY Past Questions - National Open University of Nigeria TMA Portal

NOUN TMA PHY Past Questions 2017


1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48mhz
(a) 10.24kmz
(b) 5khz
(c) 30.24hz
(d) 15khz

2. Which statement best describe the operation of a negative edge-triggered D flip-flop?
(a) The logic level at the D input is transferred to Q on NGT of CLK
(b) The output is always identical to the CLK input if the D input is high
(c) The Q output is always identical to the D input when CLK=PGT
(d) The Q output is always identical to the D input

3. Propagation delays time, tPLH is measured from the ……………..
(a) Triggering edge of the clock pulse to the high transition of the output
(b) Triggering edge of the clock pulse to the high to low transition of the output
(c) Present input to the low to high transition of the output
(d) Clear input to the high to low transition of the output

4. How is a j-k flip-flop made to toggle
(a)J=0, K=0
(b)J=1, K=0
(c)J=0, K=0
(d)J=1, K=1

5. How many flip-flop are in the 7475 1c
(a) 1
(b) 2
(c) 4
(d) 8

6. How many flip-flops are in the required to produce a divide-by-128 device
(a) 1
(b) 4
(c) 6
(d) 7

7. Which is not an altera primitive port identifier
(a) clk
(b) ena
(c) clr
(d) prn

8. The timing network that sets the output frequency of a 555 astable circuit contains
(a) Three astable resistors and used
(b) Two external resistors and two-external capacitors are used
(c) An external resistors and two-external capacitors are used
(d) No external resistor or capacitors is required

9. What is the difference b/w the enable inputs of the clock input of the 7474
(a) The 7475 is edge triggered
(b) The 7474 is edge triggered

10.The phenomenon of interpreting unwanted signals on J and K while (clock pulse) is high is called ……………
(a) Parity error checking
(b) Ones catching
(c) Digital discrimination
(d) Digital filtering

11. What is another name for a one-shot
(a) Menostable
(b) Multivibrator
(c) Bistable
(d) Astable

12. On a master-slave flip-flop when is the master enable.
· When the gate is low
· When the gate is High
· Both of the above
· Neither of the above

13.One example of the use of an S-R flip-flop is a
· Racer
· Astable oscillator
· Binary storage register
· Transition pulse generator

14.What is the difference between the 7476 and the 74 & 576
· The 7476 is master-slave, the 741576 is master slave
· The 7476 is edge-triggered, the 741576 is edge-triggered
· The 7474 is edge triggered, the 741576 is master-slave

· The 7474 is master-slave, the 741576 is-slave, the 741576 is edge-triggered
15.With regard to a D catch, …………………..
· The Q output follows the D input when EN is low
· The Q output is opposite the D input when EN is low
· The Q output follows the D input when EN is High
· The Q output flow is High regardless of SN’s input state

16. How can the cross-coupled NAND flip-flop be made to have active-high S-R inputs.
· It can’t be done
· Invert the Q outputs
· Invert the S-R inputs

17.When is a flip-flop said to be transparent.
· When the Q output is opposite the input
· When the Q output follows the input
· When you can see through the IC packaging
· When the Q input follows the output

18.A 555 operating as a multivibrator has R, of 1Mn Determine C for a pulse width of 25.
· 1.8 uf
· 18f
· 18gf
· 18nf

19.Master-slave J-X flips are called pulse triggered or level-triggered devices be clock pulse is at low level.
· True
· False

20.Which of the following is correct for D catch
· The output toggles if one of the inputs is held high
· Q outputs follows the input D when the enable is high
· Only one of the inputs can be High at a time
· The output complement follows the input when enabled

21.A J-K flip-flop is in a “nochange” condition when ……………
· J=1, K=1
· J=1, K=0
· J=0, K=1
· J=0, K=0

22.A correct output is achieved from a master slave J.K flip-flop only if input are stable while the…………..
· Clock is low
· Slave is transforming
· Flip-flop is reset
· Clock is High

23.Which of the following describes the operation of a positive edge-triggered D flip-flop.
· If both inputs are high , the output will toggle.
· The output will follow the input on the leading edge of the clock
· When both inputs are low,an invalid state exists.
· The input is toggled into the flip-flop on the leading edge of the trailing edge of the clock.

24. What does the triangle on the clock input of a J-k flip-flop mean
· Level enabled
· Edge triggered

25.A J-k flip-flops with J=1 and K=1 has a 20khz input. The output is ……………..
· Constantly
· Constantly high
· A 10khz square wave

26.The toggle condition in a master-slave J-K flip-flop means that Q and Q’ will switch to their state(s) at the ……………
· Opposite, active clock edge
· Inverted, positive clock edge
· Quiescent, Negative clock edge
· Reset, synchronous clock edge

27.An Rc circuit used in a non-retriggerable 74(2) one shot has an REXT of 49kv,and a CEXT of 0.2uf. The pulse width (fw) is approximately ……………
· 6.9as
· 6.9ms
· 69ms
· 690ms

28.On a positive edge-triggered S-R flip-flop the outputs reflects the input condition when ……………
· The clock pulse is low
· The clock pulse is high
· The Clock pulse transitions from low to high
· The clock pulse transition from high to low

29.If an active high S-V catch a 0 on the S input and a 1 on the R input and when the R inputs goes to, the catch will be ……….
· Set
· Reset
· Clear
· Invalid

30.What is the hold condition of a flip-flop?
· Both S and R inputs activated
· No active S or R input
· Only S is active
· Only R is active

31.In VHDL, how many inputs will a primitive JK flip-flop have
· 2
· 3
· 4
· 5

32.A 555 operating as a monostable multivibrator has a G =0.01uf Determine R, for a pulse width of 2ms
· 200n
· 182kn
· 91kn
· 182n

33.AD flip-flop utilizing a PGT clock is in the clear state, Which of the following input actions will cause it to change states
· CLK = NGT, D = 0
· CLK = PGT< D = 0
· Clock NGT, D = 1
· Clock PGT, D = 1

34. The symbol on this flip-flop device indicates
· Triggering takes place on the negative-going edge of the CLK pulse.
· Triggering takes place on the positive-going edge of the CLK pulse
· Triggering can take place anytime during the high level of the CLK waveform
· Triggering can take place anytime during the low level of the CLK waveform.

35. In a 555time, where 5k or resistors gravite a trigger level of ………..
· ¼ Vcc and threshold level ½ Vcc
· 1/3 Vcc and a threshold level ¾ Vcc
· 1/3 Vcc and a threshold level 2/3 Vcc
· ¼ Vcc and a threshold level ¾ Vcc

36.Does the cross-coupled NOR flip-flop have active-high or active-low and reset inputs.
· Active-High
· Active-low
· Non of the above
· All of the above
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